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FINAL
Am27C256
256 Kilobit (32,768 x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
s Fast access time -- 55 ns s Low power consumption -- 20 A typical CMOS standby current s JEDEC-approved pinout s Single +5 V power supply s 10% power supply tolerance available s 100% Flashrite programming -- Typical programming time of 4 seconds
Advanced Micro Devices
s Latch-up protected to 100 mA from -1 V to VCC + 1 V s High noise immunity s Versatile features for simple interfacing -- Both CMOS and TTL input/output compatibility -- Two line control functions s Standard 28-pin DIP, PDIP, 32-pin TSOP and PLCC packages
GENERAL DESCRIPTION
The Am27C256 is a 256K-bit ultraviolet erasable programmable read-only memory. It is organized as 32K words by 8 bits per word, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. Products are available in windowed ceramic DIP packages as well as plastic one time programmable (OTP) PDIP, TSOP, and PLCC packages. Typically, any byte can be accessed in less than 55 ns, allowing operation with high-performance microprocessors without any WAIT states. The Am27C256 offers separate Output Enable (OE) and Chip Enable (CE) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD's CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 80 mW in active mode, and 100 W in standby mode. All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The Am27C256 supports AMD's Flashrite programming algorithm (100 s pulses) resulting in typical programming time of 4 seconds.
BLOCK DIAGRAM
VCC VSS VPP
Data Outputs DQ0-DQ7
OE CE
Output Enable Chip Enable and Prog Logic Y Decoder
Output Buffers
Y Gating
A0-A14 Address Inputs
X Decoder
262,144 Bit Cell Matrix
08007H-1
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Publication# 08007 Rev. H Issue Date: May 1995
Amendment /0
AMD
PRODUCT SELECTOR GUIDE
Family Part No. Ordering Part No: VCC 5% VCC 10% Max Access Time (ns) CE (E) Access Time (ns) OE (G) Access Time (ns) -55 55 55 35 -70 70 70 40 -90 90 90 40 -120 120 120 50 -150 150 150 50 -200 200 200 50 250 250 50 Am27C256 -255
CONNECTION DIAGRAMS Top View DIP
A7 A12 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A14 A13 A8 A9 A11 OE (G) A10 CE (E) DQ7 DQ6 DQ5 DQ4 DQ3
08007H-2
PLCC
A14 VCC A13 VPP DU
4 3 2 1 32 31 30 A6 A5 A4 A3 A2 A1 A0 NC DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DQ1 DQ2 VSS DQ4 DQ5 DQ3 DU 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE (G) A10 CE (E) DQ7 DQ6
08007H-3
Notes: 1. JEDEC nomenclature is in parentheses.
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AMD
CONNECTION DIAGRAM
TSOP*
OE (G) A11 A9 A8 A13 NC A14 VCC VPP NC A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC A10 CE (E) DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 NC A0 A1 A2
08007H-4
*Contact local AMD sales office for package availability
Standard Pinout
PIN DESIGNATIONS
A0-A14 CE (E) DQ0-DQ7 OE (G) VCC VPP VSS DU = = = = = = = = Address Inputs Chip Enable Data Inputs/Outputs Output Enable Input VCC Supply Voltage Program Voltage Input Ground Don't Use
LOGIC SYMBOL
15 A0-A14
8 DQ0-DQ7
CE (E) OE (G)
08007H-5
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Am27C256
AMD
ORDERING INFORMATION UV EPROM Products
AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27C256 -55 D C B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-in TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) E = Extended Commercial (-55C to +125C) PACKAGE TYPE D = 28-Pin Ceramic DIP (CDV028)
SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER Am27C256 256 Kilobit (32,768 x 8-Bit) CMOS UV EPROM
Valid Combinations AM27C256-55 AM27C256-70 AM27C256-90 AM27C256-120 AM27C256-150 AM27C256-200 AM27C256-255 DC, DCB, DI, DIB
DC, DCB, DI, DIB, DE, DEB
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
DC, DCB, DI, DIB
Am27C256
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AMD
ORDERING INFORMATION OTP Products
AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27C256 -55 P C OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to + 85C) PACKAGE TYPE P = 28-Pin Plastic DIP (PD 028) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin TSOP (TS 032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER Am27C256 256 Kilobit (32,768 x 8-Bit) CMOS OTP EPROM
Valid Combinations JC, PC, EC AM27C256-55 AM27C256-70 AM27C256-90 JC, PC, EC, AM27C256-120 JI, PI, EI AM27C256-150 AM27C256-200 AM27C256-255
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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Am27C256
AMD
FUNCTIONAL DESCRIPTION Erasing the Am27C256
In order to clear all locations of their programmed contents, it is necessary to expose the Am27C256 to an ultraviolet light source. A dosage of 15 W sec/cm2 is required to completely erase an Am27C256. This dosage can be obtained by exposure to an ultraviolet amp-- wavelength of 2537 A--with intensity of 12,000 W/cm2 for 15 to 20 minutes. The Am27C256 should be directly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the Am27C256 and similar devices will erase with light sources having wavelengths shorter than 4000 A. Although erasure times will be much longer than with UV sources at 2537 A, exposure to fluorescent light and sunlight will eventually erase the Am27C256 and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package window should be covered by an opaque label or substance.
OE High will program that Am27C256. A high-level CE input inhibits the other Am27C256 devices from being programmed.
Program Verify
A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE at VIL, CE at VIH, and VPP between 12.5 V to 13.0 V.
Auto Select Mode
The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C 5C ambient temperature range that is required when programming the Am27C256. To activate this mode, the programming equipment must force 12.0 V 0.5 V on address like A9 of the Am27C256. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto select mode. Byte 0 (A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device code. For the Am27C256, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit.
Programming the Am27C256
Upon delivery or after each erasure the Am27C256 has all 262,144 bits in the "ONE" or HIGH state. "ZEROs" are loaded into the Am27C256 through the procedure of programming. The programming mode is entered when 12.75 V 0.25 V is applied to the VPP pin, OE is at VIH, and CE is at VIL. For programming, the data to be programmed is applied 8 bits in parallel to the data output pins. The Flashrite algorithm reduces programming time by using 100 s programming pulses and by giving each address only as many pulses as is necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum is reached. This process is repeated while sequencing through each address of the Am27C256. This part of the algorithm is done at VCC = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the entire EPROM memory is verified at VCC = VPP = 5.25 V. Please refer to Section 6 for programming flow chart and characteristics.
Read Mode
The Am27C256 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC-tOE.
Standby Mode
The Am27C256 has a CMOS standby mode which reduces the maximum VCC current to 100 A. It is placed in CMOS-standby when CE is at VCC 0.3 V. The Am27C256 also has a TTL-standby mode which reduces the maximum VCC current to 1.0 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input.
Program Inhibit
Programming of multiple Am27C256 in parallel with different data is also easily accomplished. Except for CE, all like inputs of the parallel Am27C256 may be common. A TTL low-level program pulse applied to an Am27C256 CE input with VPP = 12.75 V 0.25 V, and
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AMD
Output OR-Tieing
To accommodate multiple memory connections, a twoline control function is provided to allow for:
s Low memory power dissipation s Assurance that output bus contention will not occur
System Applications
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1-F ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7-F bulk electrolytic capacitor should be used between VCC and VSS for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.
It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in low-power standby mode and that the output pins are only active when data is desired from a particular memory device.
MODE SELECT TABLE
Mode Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Auto Select (Note 3) Manufacturer Code Device Code Pins CE VIL X VIH VCC + 0.3 V VIL VIH VIH VIL VIL OE VIL VIH X X VIH VIL VIH VIL VIL A0 X X X X X X X VIL VIH A9 X X X X X X X VH VH VPP X X X X VPP VPP VPP X X Outputs DOUT High-Z High-Z High-Z DIN DOUT High-Z 01H 10H
Notes: 1. VH = 12.0 V + 0.5 V 2. X = Either VIH or VIL 3. A1-A8 = A10-A14 = VIL 4. See DC Programming Characteristics for VPP voltage during programming.
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Am27C256
AMD
ABSOLUTE MAXIMUM RATINGS
Storage Temperature OTP Products . . . . . . . . . . . . . . . -65C to +125C All Other Products . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Voltage with Respect To VSS All pins except A9,VPP,VCC (Note 1) . . . . . . . . . . . . . . . -0.6 V to VCC + 0.5 V A9 and VPP (Note 2) . . . . . . . . . . -0.6 V to +13.5 V VCC . . . . . . . . . . . . . . . . . . . . . . . -0.6 V to +7.0 V
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During transitions, the inputs may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input andI/O pins is VCC + 0.5 V which may overshoot to VCC + 2.0 V for periods up to 20 ns. 2. For A9 and VPP the minimum DC input is -0.5 V. During transitions, A9 and VPP may overshoot VSS to -2.0 V for periods of up to 20 ns. A9 and VPP must not exceed 13.5 V for any period of time. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . 0C to +70C Industrial (I) Devices Ambient Temperature (TA) . . . . . -40C to +85C Extended Commercial (E) Devices Ambient Temperature (TA) . . . . -55C to +125C Supply Read Voltages VCC for Am27C256-XX5 . . . . . +4.75 V to +5.25 V VCC for Am27C256-XX0 . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Am27C256
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AMD
DC CHARACTERISTICS over operating range unless otherwise specified. (Notes 1, 2 and 4)
Parameter Symbol VOH VOL VIH VIL ILI ILO Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VIN = 0 V to +VCC VOUT = 0 V to +VCC CE = VIL, f = 10 MHz, IOUT = 0 mA CE = VIH CE = VCC 0.3 V CE = OE = VIL, VPP = VCC C/I Devices E Devices ICC1 ICC2 ICC3 IPP1 VCC Active Current (Note 3) VCC TTL Standby Current VCC CMOS Standby Current VPP Current During Read Test Conditions IOH = -400 A IOL = 2.1 mA 2.0 -0.5 Min 2.4 0.45 VCC + 0.5 +0.8 1.0 1.0 5.0 25 1.0 100 100 mA mA A A Max Unit V V V V A A
Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. Caution: The Am27C256 must not be removed from (or inserted into) a socket when VCC or VPP is applied. 3. ICC1 is tested with OE = VIH to simulate open outputs. 4. Minimum DC Input Voltage is -0.5 V. During transitions, the inputs may overshoot to -2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.
30 25 20 15 10 1 2 3 4 5 6 7 8 9 10 Frequency in MHz
30 25 20 15 10 -75 -50 -25 0
Supply Current in mA
Supply Current in mA
25
50
75 100 125 150
Temperature in C
Figure 1. Typical Supply Current vs. Frequency VCC = 5.5 V, T = 25C
08007H-6
Figure 2. Typical Supply Current vs. Temperature VCC = 5.5 V, f = 10 MHz
08007H-7
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Am27C256
AMD
CAPACITANCE
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 0 VOUT = 0 CDV028 Typ 8 8 Max 12 12 PL 032 Typ 8 8 Max 12 12 PD 028 Typ 6 8 Max 10 10 TS 032 Typ 10 12 Max 12 14 Unit pF pF
Notes: 1. This parameter is only sampled and not 100% tested. 2. TA = +25C, f = 1 MHz.
SWITCHING CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 3 and 4)
Parameter Symbols JEDEC tAVQV tELQV tGLQV tEHQZ, tGHQZ Standard tACC tCE tOE tDF (Note 2) Am27C256 Parameter Description Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable HIGH or Output Enable HIGH, whichever comes first, to Output Float Output Hold from Addresses, CE, or OE, whichever occurred first Test Conditions CE = OE = VIL OE = VIL CE = VIL Min Max Min Max Min Max Min Max -55 - 55 - 55 - 35 - 25 -70 - 70 - 70 - 40 - 25 -90 - 90 - 90 - 40 - 25 -120 - 120 - 120 - 50 - 30 -150 - 150 - 150 - 50 - 30 -200 - 200 - 200 - 50 - 30 -255 - 250 - 250 - 50 - 30 Unit ns ns ns ns
tAXQX
tOH
Min Max
0 -
0 -
0 -
0 -
0 -
0 -
0 -
ns
Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. This parameter is only sampled and not 100% tested. 3. Caution: The Am27C256 must not be removed from (or inserted into) a socket or board when VPP or VCC is applied. 4. For the -55 and -70: Output Load: 1 TTL gate and CL = 30 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0 V to 3 V Timing Measurement Reference Level: 1.5 V for inputs and outputs For all other versions: Output Load: 1 TTL gate and CL = 100 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0.45 V to 2.4 V Timing Measurement Reference Level: 0.8 V and 2 V inputs and outputs
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AMD
SWITCHING TEST CIRCUIT
2.7 k Device Under Test +5.0 V
CL
6.2 k
Diodes = IN3064 or Equivalent
CL = 100 pF including jig capacitance (30 pF for -55, -70)
08007H-8
SWITCHING TEST WAVEFORM
2.4 V 0.45 V Input Output 3V 1.5 V 0V Input Output
08007H-9
2.0 V 0.8 V
Test Points
2.0 V 0.8 V
Test Points
1.5 V
AC Testing: Inputs are driven at 2.4 V for a logic "1" and 0.45 V for a logic "0". Input pulse rise and fall times are 20 ns.
AC Testing: Inputs are driven at 3.0 V for a logic "1" and 0 V for a logic "0". Input pulse rise and fall times are 20 ns for -55 and -70.
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Am27C256
AMD
KEY TO SWITCHING TEST WAVEFORMS
WAVEFORM INPUTS Must Be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will Be Steady Will Be Changing from H to L Will Be Changing from L to H Changing State Unknown Center Line is High Impedence "Off" State KS000010
SWITCHING WAVEFORMS
2.4 Addresses 0.45
2.0 0.8
Addresses Valid
2.0 0.8
CE tCE OE tOE tOH Valid Output
08007H-10
Output
High Z
tACC (Note 1)
tDF (Note 2) High Z
Notes: 1. OE may be delayed up to tACC-tOE after the falling edge of the addresses without impact on tACC. 2. tDF is specified from OE or CE, whichever occurs first.
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